Integrated circuits (ICs) continue to scale dimensionally. Over recent generations of silicon-based CMOS transistors, various techniques have been employed to obtain higher transistor drive current as dimensions shrink. Tensile strain in the channel can reduce the effective mass of charge carriers in an n-channel transistor. Compressive strain in a channel can reduce the effective mass of charge carriers in a p-channel transistor. With reductions in effective mass, charge carrier velocity increases and drive current improves. Transistor channels have been strained by introducing various stressors proximate to the channel, for example highly-stressed Si3N4 liners have been deposited over transistors, and/or source/drain regions with crystal lattice mismatch have been utilized.
However, the levels of stress required to induce sufficient channel strain for band splitting to occur is high, typically in the 1-2 MPa range. While such high stress could be achieved by various means in planar devices, it is more difficult to do so in non-planar, finFET architectures. This is particularly true for n-channel silicon devices as it is difficult to incorporate material having a lattice constant significantly smaller than that of silicon. Silicon doped with 1-2% C (Si:C), for example, typically does not introduce sufficient channel strain.
Transistor architectures, and methods of fabricating such transistors, capable of imparting significant strain in a transistor channel crystal, particularly tensile strain, are therefore advantageous.